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[RV64_DYNAREC] Optimized a few AVX opcodes #4601

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Merged
ptitSeb merged 1 commit into from
Oct 26, 2026
Merged

[RV64_DYNAREC] Optimized a few AVX opcodes #4601

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55 changes: 48 additions & 7 deletions src/dynarec/rv64/dynarec_rv64_avx_0f_vector.c
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Original file line number Diff line number Diff line change
Expand Up @@ -456,14 +456,16 @@ uintptr_t dynarec64_AVX_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t
GETGY_empty_vector(v0);
q2 = fpu_get_scratch(dyn);
d0 = fpu_get_scratch(dyn);
VMFEQ_VV(q2, q0, q0, VECTOR_UNMASKED);
VMFEQ_VV(d0, q1, q1, VECTOR_UNMASKED);
VMAND_MM(q2, q2, d0);
switch (u8 & 0xf) {
case 0x0: VMFEQ_VV(VMASK, q0, q1, VECTOR_UNMASKED); break;
case 0x1: VMFLT_VV(VMASK, q0, q1, VECTOR_UNMASKED); break;
case 0x2: VMFLE_VV(VMASK, q0, q1, VECTOR_UNMASKED); break;
case 0x3: VMNAND_MM(VMASK, q2, q2); break;
case 0x3:
VMFEQ_VV(q2, q0, q0, VECTOR_UNMASKED);
VMFEQ_VV(d0, q1, q1, VECTOR_UNMASKED);
VMAND_MM(q2, q2, d0);
VMNAND_MM(VMASK, q2, q2);
break;
case 0x4:
VMFEQ_VV(d0, q0, q1, VECTOR_UNMASKED);
VMNAND_MM(VMASK, d0, d0);
Expand All @@ -476,8 +478,16 @@ uintptr_t dynarec64_AVX_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t
VMFLE_VV(d0, q0, q1, VECTOR_UNMASKED);
VMNAND_MM(VMASK, d0, d0);
break;
case 0x7: VMAND_MM(VMASK, q2, q2); break;
case 0x7:
VMFEQ_VV(q2, q0, q0, VECTOR_UNMASKED);
VMFEQ_VV(d0, q1, q1, VECTOR_UNMASKED);
VMAND_MM(q2, q2, d0);
VMAND_MM(VMASK, q2, q2);
break;
case 0x8:
VMFEQ_VV(q2, q0, q0, VECTOR_UNMASKED);
VMFEQ_VV(d0, q1, q1, VECTOR_UNMASKED);
VMAND_MM(q2, q2, d0);
VMFEQ_VV(d0, q0, q1, VECTOR_UNMASKED);
VMNAND_MM(VMASK, q2, q2);
VMOR_MM(VMASK, VMASK, d0);
Expand All @@ -490,15 +500,28 @@ uintptr_t dynarec64_AVX_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t
VMFLT_VV(d0, q1, q0, VECTOR_UNMASKED);
VMNAND_MM(VMASK, d0, d0);
break;
case 0xb: VMXOR_MM(VMASK, q2, q2); break;
case 0xb:
VMFEQ_VV(q2, q0, q0, VECTOR_UNMASKED);
VMFEQ_VV(d0, q1, q1, VECTOR_UNMASKED);
VMAND_MM(q2, q2, d0);
VMXOR_MM(VMASK, q2, q2);
break;
case 0xc:
VMFEQ_VV(q2, q0, q0, VECTOR_UNMASKED);
VMFEQ_VV(d0, q1, q1, VECTOR_UNMASKED);
VMAND_MM(q2, q2, d0);
VMFEQ_VV(d0, q0, q1, VECTOR_UNMASKED);
VMNAND_MM(VMASK, d0, d0);
VMAND_MM(VMASK, VMASK, q2);
break;
case 0xd: VMFLE_VV(VMASK, q1, q0, VECTOR_UNMASKED); break;
case 0xe: VMFLT_VV(VMASK, q1, q0, VECTOR_UNMASKED); break;
case 0xf: VMXNOR_MM(VMASK, q2, q2); break;
case 0xf:
VMFEQ_VV(q2, q0, q0, VECTOR_UNMASKED);
VMFEQ_VV(d0, q1, q1, VECTOR_UNMASKED);
VMAND_MM(q2, q2, d0);
VMXNOR_MM(VMASK, q2, q2);
break;
}
VXOR_VV(v0, v0, v0, VECTOR_UNMASKED);
VMERGE_VIM(v0, v0, 0x1f);
Expand All @@ -508,6 +531,24 @@ uintptr_t dynarec64_AVX_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t
INST_NAME("VSHUFPS Gx, Vx, Ex, Ib");
nextop = F8;
GETVY_vector(q0, VECTOR_SEW32);
if (!vex.l && MODREG && ((nextop & 7) + (rex.b << 3)) == vex.v) {
u8 = F8;
MOV64x(x4, (uint64_t)(u8 & 3) | ((uint64_t)((u8 >> 2) & 3) << 16) | ((uint64_t)((u8 >> 4) & 3) << 32) | ((uint64_t)((u8 >> 6) & 3) << 48));
vector_vsetvli(dyn, ninst, x1, VECTOR_SEW64, VECTOR_LMUL1, 1);
q2 = fpu_get_scratch(dyn);
VMV_S_X(q2, x4);
avx_set_vector_width(dyn, ninst, x1, VECTOR_SEW32, 16);
GETGY_empty_vector(v0);
if (v0 == q0) {
v2 = fpu_get_scratch(dyn);
VRGATHEREI16_VV(v2, q0, q2, VECTOR_UNMASKED);
v0 = v2;
} else {
VRGATHEREI16_VV(v0, q0, q2, VECTOR_UNMASKED);
}
PUTGY_vector(v0, VECTOR_SEW32);
break;
}
GETEY_vector(q1, 1, VECTOR_SEW32);
u8 = F8;
GETGY_empty_vector(v0);
Expand Down
8 changes: 2 additions & 6 deletions src/dynarec/rv64/dynarec_rv64_avx_66_0f38_vector.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1167,12 +1167,8 @@ uintptr_t dynarec64_AVX_66_0F38_vector(dynarec_rv64_t* dyn, uintptr_t addr, uint
GETVY_vector(q0, sew);
GETEY_vector(q1, 0, sew);
GETGY_vector(q2, sew);
GETGY_empty_vector(v0);
VEC_SRC_KEEP(q0, v0);
VEC_SRC_KEEP(q1, v0);
VMV_V_V(v0, q2);
VFMACC_VV(v0, q0, q1, VECTOR_UNMASKED);
PUTGY_vector(v0, sew);
VFMACC_VV(q2, q0, q1, VECTOR_UNMASKED);
PUTGY_vector(q2, sew);
break;
case 0xB6:
INST_NAME("VFMADDSUB231PS/D Gx, Vx, Ex");
Expand Down
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