Skip to content

[RV64_DYNAREC] Fix width error for VMOVSS #4600

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
ptitSeb merged 1 commit into from
Oct 26, 2026
Merged

[RV64_DYNAREC] Fix width error for VMOVSS #4600

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 1 addition & 3 deletions src/dynarec/rv64/dynarec_rv64_avx_f3_0f_vector.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -78,13 +78,11 @@ uintptr_t dynarec64_AVX_F3_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintpt
avx_load_reg_vector(dyn, ninst, x1, q0, gd, 16, VECTOR_SEW32);
if (MODREG) {
ed = (nextop & 7) + (rex.b << 3);
q1 = fpu_get_scratch(dyn);
avx_load_reg_vector(dyn, ninst, x1, q1, ed, 16, VECTOR_SEW32);
q2 = fpu_get_scratch(dyn);
avx_load_reg_vector(dyn, ninst, x1, q2, vex.v, 16, VECTOR_SEW32);
VFMV_F_S(d0 = fpu_get_scratch(dyn), q0);
VFMV_S_F(q2, d0);
avx_store_reg_vector(dyn, ninst, x1, q2, ed, 32, VECTOR_SEW32);
avx_store_reg_vector(dyn, ninst, x1, q2, ed, 16, VECTOR_SEW32);
} else {
addr = geted(dyn, addr, ninst, nextop, &ed, x2, x3, &fixedaddress, rex, NULL, 0, 0);
VFMV_F_S(d0 = fpu_get_scratch(dyn), q0);
Expand Down
Loading