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edge: fix psoc-edge I2C clock and expose Wire on the header - #38
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Looks good :) |
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Both I2C clock dividers (peri0_group1_16bit_1 for Wire, peri0_group1_16bit_3 for Wire1) were set to clock-div = <1>, feeding the SCB with 100 MHz and driving SCL at ~6.25 MHz instead of 100 kHz, which broke I2C communication (test_wire_connected1_pingpong). The PSoC Edge I2C driver does not derive the SCB clock from clock-frequency; it uses the devicetree divider with fixed 16x oversampling. Set clock-div = <63>: 100 MHz / 63 = ~1.59 MHz SCB clock (within the PDL 1.55-3.2 MHz range for a 100 kHz master), ~99 kHz SCL. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> Signed-off-by: AkshayChandra-IFX <akshaychandra.nagzarkar@infineon.com>
SCB0 (P8_0/P8_1) is the internal sensor bus and not on a header, so Wire could not be tested. Map Wire to SCB11 on P17_2/P17_3; mark test_wire_connected1_pingpong as passing. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> Signed-off-by: AkshayChandra-IFX <akshaychandra.nagzarkar@infineon.com>
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IFX-Anusha
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| clocks = <&peri0_group1_16bit_1>; | ||
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| pinctrl-0 = <&p17_2_scb11_i2c_scl &p17_3_scb11_i2c_sda>; |
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Here you have updated but still variant.h points to the #define SDA 43 /< P8_1 */
#define SCL 42 /< P8_0 */. So that should be changed right?
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yes. thanks to point out. This is missed, i will update it!
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Description
Both I2C clock dividers were set to
clock-div = <1>, which ran SCL at ~6.25 MHz instead of 100 kHz. The PSoC Edge I2C driver uses this divider directly and ignoresclock-frequency. This PR setsclock-div = <63>for Wire and Wire1, giving ~99 kHz SCL.Wirewas on SCB0 (P8_0/P8_1), the internal sensor bus, which isn't on any header. This PR moves it to SCB11 on P17_2/P17_3, next to Wire1, so the loopback test can be wired.A couple of things to keep in mind:
Wireno longer talks to the on-board IMU, pressure and humidity sensors.Wireon its own needs external pull-ups.Related Issue
None.
Context
Wiring: P17_2 ↔ P17_0 (SCL), P17_3 ↔ P17_1 (SDA)